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FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Table 21: Allowed Timer/Counter Mode Combinations
Timer 1
Mode 0
Mode 1
Mode 2
Timer 0 - mode 0
Timer 0 - mode 1
Timer 0 - mode 2
Yes
Yes
Not allowed
Yes
Yes
Not allowed
Yes
Yes
Yes
Table 22: TMOD Register Bit Description (SFR 0x89)
Bit
Symbol
Function
Timer/Counter 1:
TMOD[7] Gate
If TMOD[7] is set, external input signal control is enabled for Counter 0.
external gate control. The TR1 bit in the TCON register (SFR 0x88) must
also be set in order for Counter 1 to increment.
With these settings Counter 1 is incremented on every falling edge of the
logic signal applied to one or more of the interrupt sources controlled by
the DI_RBP , DIO_R1 , … DIO_RXX registers.
TMOD[6]
TMOD[5:4]
C/T
M1:M0
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as a
timer.
Selects the mode for Timer/Counter 1 as shown in Table 20 .
Timer/Counter 0:
TMOD[3] Gate
If TMOD[3] is set, external input signal control is enabled for Counter 0.
external gate control. The TR0 bit in the TCON register (SFR 0x88) must
also be set in order for Counter 0 to increment.
With these settings Counter 0 is incremented on every falling edge of the
logic signal applied to one or more of the interrupt sources controlled by
the DI_RBP , DIO_R1 , … DIO_RXX registers.
TMOD[2]
TMOD[1:0]
C/T
M1:M0
Selects timer or counter operation. When set to 1, a counter operation is
performed. When cleared to 0, the corresponding register will function as
a timer.
Selects the mode for Timer/Counter 0, as shown in Table 20 .
Table 23: The TCON Register Bit Functions (SFR 0x88)
Bit
TCON[7]
TCON[6]
TCON[5]
TCON[4]
TCON[3]
TCON[2]
TCON[1]
TCON[0]
Rev 2
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Function
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when an
interrupt is processed.
Timer 1 run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt
is processed.
Timer 0 Run control bit. If cleared, Timer 0 stops.
Interrupt 1 edge flag is set by hardware when the falling edge on external
pin int1 is observed. Cleared when an interrupt is processed.
Interrupt 1 type control bit. Selects either the falling edge or low level on
input pin to cause an interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on external
pin int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. Selects either the falling edge or low level on
input pin to cause interrupt.
29
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